Special Session #1
Design and Analysis of Nonlinear Circuits and Networks
Organizer: Yoshifumi Nishio (Tokushima University, Japan)
Abstract
In recent years, nonlinear circuits and networks become more and more important, because intelligent and flexible systems for future electronic systems require complex nonlinear circuits and networks.
From the beginning of the 20th century, plenty of design and analysis methods for nonlinear circuits and networks have been developed over 100 years.
However, we need more powerful tools to design low cost power electronic circuits, to analyze large scale complex nonlinear networks, and to realize more intelligent artificial neural networks.
In this special session, 6 papers are invited to show examples of recent works on design and analysis of such nonlinear circuits and networks.
In recent years, nonlinear circuits and networks become more and more important, because intelligent and flexible systems for future electronic systems require complex nonlinear circuits and networks.
From the beginning of the 20th century, plenty of design and analysis methods for nonlinear circuits and networks have been developed over 100 years.
However, we need more powerful tools to design low cost power electronic circuits, to analyze large scale complex nonlinear networks, and to realize more intelligent artificial neural networks.
In this special session, 6 papers are invited to show examples of recent works on design and analysis of such nonlinear circuits and networks.
Special Session #2
Design, Analysis and Tools for Integrated Circuits and Systems (DATICS)
Organizer: Ka Lok Man (Xi’an Jiaotong-Liverpool University, China)
Abstract
DATICS workshops/special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC’21 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade.
The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC’21 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences.
DATICS workshops/special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC’21 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade.
The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC’21 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences.
Special Session #3
Emerging Technologies for Energy-efficient AI Processor
Organizer: Liang Chang (University of Electronic Science and Technology of China, China)
Abstract
The deployment of artificial intelligent algorithm (AI) onto edge devices has limited by the performance and energy efficiency of AI processor. In this session, we will discuss several emerging technologies to solve the performance and energy issues.
First, the SRAM-based Computing-in-Memory (CIM) chips has demonstrated high performance and high energy-efficient, including topic “Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices” and “Energy-efficient CIM SoC design for edge AI devices”. Secondly, the domain specific AI processor can be developed by the specific architecture. Thirdly, the emerging nonvolatile memory can also be used to design the AI processor from both architecture and circuit levels. We hope to demonstrate several state-of-the-art developments toward energy-efficient AI processor
The deployment of artificial intelligent algorithm (AI) onto edge devices has limited by the performance and energy efficiency of AI processor. In this session, we will discuss several emerging technologies to solve the performance and energy issues.
First, the SRAM-based Computing-in-Memory (CIM) chips has demonstrated high performance and high energy-efficient, including topic “Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices” and “Energy-efficient CIM SoC design for edge AI devices”. Secondly, the domain specific AI processor can be developed by the specific architecture. Thirdly, the emerging nonvolatile memory can also be used to design the AI processor from both architecture and circuit levels. We hope to demonstrate several state-of-the-art developments toward energy-efficient AI processor
Special Session #4
Deep Submicron Technology Driven Digital and Analog Design Methodologies and Verfications
Organizer: Taewhan Kim (Seoul National University, Korea)
Abstract
As the process technology advances to deep submicron regime, new challenging issues come out today. In this special session, a set of solutions and survey regarding the most challenging design methodology and verification issues are presented. Precisely, this session covers four prominent items: (1) fast and reliable formal verification for analog circuits, (2) fast simulation methodology for optimizing analog circuit structures, (3) viable low power technique of DRAM refresh mechanism to cope with DRAM technology scaling, and (4) survey on challenging issues of DTCO (design-technology-co-optimization) methodology towards deep submicron interconnect technology.
As the process technology advances to deep submicron regime, new challenging issues come out today. In this special session, a set of solutions and survey regarding the most challenging design methodology and verification issues are presented. Precisely, this session covers four prominent items: (1) fast and reliable formal verification for analog circuits, (2) fast simulation methodology for optimizing analog circuit structures, (3) viable low power technique of DRAM refresh mechanism to cope with DRAM technology scaling, and (4) survey on challenging issues of DTCO (design-technology-co-optimization) methodology towards deep submicron interconnect technology.
Special Session #5
Emerging techniques for neural networks, non-linear, bio-sensing, and wearable circuits and systems
Organizer: Kyeong-Sik Min (Kookmin University, Korea)
Abstract
In this special session, emerging techniques of neuromorphic, non-linear, bio-sensing, wearable, etc. are discussed and presented. Using emerging devices such as memristors and spin-orbit torque MRAMs, potential solutions are presented for neuromorphic, bio-sensing, etc. And, a non-linear-circuit-based theory is explained as a potential tool for understanding brain’s behaviors. And, a wearable technique is also discussed for energy harvesting in this special session.
In this special session, emerging techniques of neuromorphic, non-linear, bio-sensing, wearable, etc. are discussed and presented. Using emerging devices such as memristors and spin-orbit torque MRAMs, potential solutions are presented for neuromorphic, bio-sensing, etc. And, a non-linear-circuit-based theory is explained as a potential tool for understanding brain’s behaviors. And, a wearable technique is also discussed for energy harvesting in this special session.
Special Session #6
Advanced AI Chip Design
Organizer: Joo-Young Kim (KAIST, Korea)
Abstract
Artificial intelligence (AI) and machine learning (ML) technology are revolutionizing many fields of study and a wide range of industry sectors such as information technology, mobile communication, automotive, and manufacturing. As more industries are adopting the technology, we face an ever-increasing demand for a new type of hardware that enables faster and more energy-efficient processing for AI workloads.
In this special session, we invite prominent scholars from AI Semiconductor Systems (AISS) Research Center, headquartered at KAIST, South Korea, to hear about the latest AI chip design and system implementation. The event will cover various aspects of AI chip design, from hardware issues such as circuits and architectures to software issues such as compilers and programming. The target audience will be graduate students, chip designers, hardware engineers, and researchers interested in designing AI chips with a holistic view.
Artificial intelligence (AI) and machine learning (ML) technology are revolutionizing many fields of study and a wide range of industry sectors such as information technology, mobile communication, automotive, and manufacturing. As more industries are adopting the technology, we face an ever-increasing demand for a new type of hardware that enables faster and more energy-efficient processing for AI workloads.
In this special session, we invite prominent scholars from AI Semiconductor Systems (AISS) Research Center, headquartered at KAIST, South Korea, to hear about the latest AI chip design and system implementation. The event will cover various aspects of AI chip design, from hardware issues such as circuits and architectures to software issues such as compilers and programming. The target audience will be graduate students, chip designers, hardware engineers, and researchers interested in designing AI chips with a holistic view.
Special Session #7
Architecture Design and Optimization of CNN accelerators for Edge AI Applications
Organizer: Hyungwon Kim (Chungbuk National University, Korea)
Abstract
Recently the AI industry is experiencing ever-growing demand for making CNN inference and even training operations conducted in low power devices for mobile and edge applications such as autonomous vehicles, smart factory, mobile robots, and mobile phones. While extensive research has been reported in CNN accelerator research areas ranging from CNN model, compression, and hardware architecture, the state of the art is still far from the level of performance that can realize true mobile AI devices. This session presents a collection of new research approaches towards making CNN models and accelerator architectures better optimized for higher inference speed at lower energy consumption with little sacrifice of accuracy. The session covers various topics including framework for reinforcement learning, optimal CNN accelerator design methodology, light weight CNN for mobile signal processing, and analog-digital mixed signal approach to ultra-low power CNN accelerators.
Recently the AI industry is experiencing ever-growing demand for making CNN inference and even training operations conducted in low power devices for mobile and edge applications such as autonomous vehicles, smart factory, mobile robots, and mobile phones. While extensive research has been reported in CNN accelerator research areas ranging from CNN model, compression, and hardware architecture, the state of the art is still far from the level of performance that can realize true mobile AI devices. This session presents a collection of new research approaches towards making CNN models and accelerator architectures better optimized for higher inference speed at lower energy consumption with little sacrifice of accuracy. The session covers various topics including framework for reinforcement learning, optimal CNN accelerator design methodology, light weight CNN for mobile signal processing, and analog-digital mixed signal approach to ultra-low power CNN accelerators.
Special Session #8
Advances in High-Speed Analog-to-digital Converters
Organizer: Liang Qi (Shanghai Jaio Tong University, China)
Abstract
In recent years, emerging communication and radar applications have been developed rapidly. Analog-to-digital Converters (ADCs) are key building block in such systems. First, it needs to support higher signal bandwidth with a low noise spectral density (NSD). Second, the power consumption of ADC needs to be limited to allow practical thermal management. Therefore, it becomes challenging to implement ADCs satisfying higher speed while achieving low NSD and high power efficiency. Moreover, in terms of different scenarios, the performance focus is different for ADCs. Hence, the well-suited solution results in various ADC architectures, including Nyquist and noise-shaped ADCs.
On the other hand，over the past several years, it appears as the sustainable increasing in the speed of ADCs. This trend is the result of faster CMOS process and innovative ways to use this technology. This special session would showcase different advances in high-speed ADCs, including 1) innovative design circuitry methodology, 2) architectural improvements, 3) more elaborate calibration circuitry, 4) machine learning concepts employed for ADCs, etc.
In recent years, emerging communication and radar applications have been developed rapidly. Analog-to-digital Converters (ADCs) are key building block in such systems. First, it needs to support higher signal bandwidth with a low noise spectral density (NSD). Second, the power consumption of ADC needs to be limited to allow practical thermal management. Therefore, it becomes challenging to implement ADCs satisfying higher speed while achieving low NSD and high power efficiency. Moreover, in terms of different scenarios, the performance focus is different for ADCs. Hence, the well-suited solution results in various ADC architectures, including Nyquist and noise-shaped ADCs.
On the other hand，over the past several years, it appears as the sustainable increasing in the speed of ADCs. This trend is the result of faster CMOS process and innovative ways to use this technology. This special session would showcase different advances in high-speed ADCs, including 1) innovative design circuitry methodology, 2) architectural improvements, 3) more elaborate calibration circuitry, 4) machine learning concepts employed for ADCs, etc.
Special Session #9
Energy-Efficient Memory-Centric Accelerator Design for Mobile/Edge AI
Organizer: Po-Tsang Huang (National Yang Ming Chiao Tung University, Taiwan)
Yung Du (Nanjing University, China)
Abstract
Deep neural networks (DNN) are widely used in feature classification, recommender systems and image recognition. Nevertheless, Deep neural networks are difficult to be fully deployed to edge/mobile/IoT devices because of both memory-intensive and computation-intensive workloads. The energy efficiency of DNNs s is dominated by convolution computation and off-chip memory (DRAM) accesses, especially for DRAM accesses. Therefore, we will discuss energy-efficient memory-centric accelerator design concept for mobile/edge deep-learning applications in this special session.
Accordingly, we will invite 5-6 high-quality papers from compressed compact network models, accelerator design with deep compression networks, interconnection architecture, near-memory computing and computation-in-meomory circuits.
Deep neural networks (DNN) are widely used in feature classification, recommender systems and image recognition. Nevertheless, Deep neural networks are difficult to be fully deployed to edge/mobile/IoT devices because of both memory-intensive and computation-intensive workloads. The energy efficiency of DNNs s is dominated by convolution computation and off-chip memory (DRAM) accesses, especially for DRAM accesses. Therefore, we will discuss energy-efficient memory-centric accelerator design concept for mobile/edge deep-learning applications in this special session.
Accordingly, we will invite 5-6 high-quality papers from compressed compact network models, accelerator design with deep compression networks, interconnection architecture, near-memory computing and computation-in-meomory circuits.
Special Session #10
Circuits and Systems for Smart Vision
Organizer: Xin Lou (Shanghai Tech University, China)
Abstract
Computer vision technologies are widely used in various applications nowadays. Circuits and systems are needed to support these vision technologies. This session will focus on the design circuits and systems for vision application, including algorithm, architecture, circuits, etc.
Computer vision technologies are widely used in various applications nowadays. Circuits and systems are needed to support these vision technologies. This session will focus on the design circuits and systems for vision application, including algorithm, architecture, circuits, etc.
Special Session #11
Advances in Biomedical sensor Interface: Wearable and Implantable
Organizer: Mingyi Chen (Shanghai Jiao Tong University, China)
Abstract
The increasing availability of wearable or implantable biopotential acquisition system introduces enormous biomedical applications for personal healthcare, clinical diagnostic, and treatment. The secure,real-time monitoring vital physiological signals provided by the acquisition system, such as electrophysiological signal, temperature, oxygen saturation level, allow early predication, rapid diagnostics and swift intervention for critical medical conditions, including but not limited to cardiovascular disease, neural disorder, stoke, cancers.
One of the most crucial blocks of the acquisition system is the biomedical sensor interface, with anever-increasing demand for superior performance in terms of noise, area, power dissipation and linearity. In recent years, the sensor interface that is capable of performing artificial intelligence (AI) based signal processing for the purpose of biomedical signal reasoning, classification and decision, is becoming increasingly popular. The hardware implementation for high-accuracy AI signal processing with minimum power consumption overhead is still challenging up-to-date.
In this special session, four papers have been presented with regarding to the advances in biomedical sensor Interface in both Wearable and Implantable applications. The titles and Abstracts of the papers are shown in the following sections.
The increasing availability of wearable or implantable biopotential acquisition system introduces enormous biomedical applications for personal healthcare, clinical diagnostic, and treatment. The secure,real-time monitoring vital physiological signals provided by the acquisition system, such as electrophysiological signal, temperature, oxygen saturation level, allow early predication, rapid diagnostics and swift intervention for critical medical conditions, including but not limited to cardiovascular disease, neural disorder, stoke, cancers.
One of the most crucial blocks of the acquisition system is the biomedical sensor interface, with anever-increasing demand for superior performance in terms of noise, area, power dissipation and linearity. In recent years, the sensor interface that is capable of performing artificial intelligence (AI) based signal processing for the purpose of biomedical signal reasoning, classification and decision, is becoming increasingly popular. The hardware implementation for high-accuracy AI signal processing with minimum power consumption overhead is still challenging up-to-date.
In this special session, four papers have been presented with regarding to the advances in biomedical sensor Interface in both Wearable and Implantable applications. The titles and Abstracts of the papers are shown in the following sections.
Special Session #12
Future Many-Core Computing
Organizer: Kun-Chih Chen (National Sun Yat-sen University, Taiwan)
Zhonghai Lu (KTH Royal Institute of Technology, Sweden)
Abstract
Many-core systems are widely used in many fields and beneficial to the intelligent computing technology. Because of the complex on-chip interconnection and high function density, the advantage of high-performance bringing from multi-core system are counteracted. Therefore, many novel multi-core architectures and interconnections, such as 3D IC, Network-on-Chip (NoC), are investigated in recent decade. However, some new design issues are raised by applying these new design methodologies. For example, high computing density leads to worse thermal issue; high-complex function integration makes the time-to-market become longer. In addition, some modern applications, such as AI computing, also need a new computing process due to the intrinsic data reuse characteristic. This special session is motivated by these challenges and aims at attracting contributions on efficient design solutions for optimizing the computing efficiency. The topics of interest include, but not limited to:
–Many-core architecture for performance optimization (e.g., NoC, 3D IC, etc.)
–Many-core computing and acceleration for AI algorithms
–Automatic design methodology and tool for multi-/many-core system design
–Emerging issues on many-core architectures and systems (e.g., thermal, power, etc.)
–New technologies (memristors, optical connections, etc.) for and their impact on many-core computing and AI accelerators
Many-core systems are widely used in many fields and beneficial to the intelligent computing technology. Because of the complex on-chip interconnection and high function density, the advantage of high-performance bringing from multi-core system are counteracted. Therefore, many novel multi-core architectures and interconnections, such as 3D IC, Network-on-Chip (NoC), are investigated in recent decade. However, some new design issues are raised by applying these new design methodologies. For example, high computing density leads to worse thermal issue; high-complex function integration makes the time-to-market become longer. In addition, some modern applications, such as AI computing, also need a new computing process due to the intrinsic data reuse characteristic. This special session is motivated by these challenges and aims at attracting contributions on efficient design solutions for optimizing the computing efficiency. The topics of interest include, but not limited to:
–Many-core architecture for performance optimization (e.g., NoC, 3D IC, etc.)
–Many-core computing and acceleration for AI algorithms
–Automatic design methodology and tool for multi-/many-core system design
–Emerging issues on many-core architectures and systems (e.g., thermal, power, etc.)
–New technologies (memristors, optical connections, etc.) for and their impact on many-core computing and AI accelerators