Tutorials

Abstract
Intelligence is moving towards edge devices. Increased computing power, sensor data, and improved artificial intelligence (AI) algorithms are the driving trends towards the on-device AI. A few examples are smartphones, automobiles, robots, drones. Therefore, on-device AI has been an emerging system on chip (SoC) technology. The on-device AI has remarkably implemented the connected devices, including automobiles, HD cameras, smartphones, wearables, and other IoT devices. In addition, the on-device inference has lower latency and increased privacy as compared to the cloud-based paradigm. However, such intelligent devices require efficient hardware. Because such compute-intensive tasks on the smaller devices require optimization of the computation power and energy consumption. This tutorial will focus on the overview, challenges, and multifaceted applications of the AI accelerators in the SoC paradigm. In tutorial session #1, we will describe the training and inference requirements of the on-device AI accelerators. In tutorial session #2, we will provide insight into the AI accelerators for future autonomous vehicles (FAVs).

Abstract
In tutorial session #1-2 will focus on emerging trends and technologies in AI acceleration for Future Autonomous Vehicles. Here, we will describe the training and inference requirements of the on-board hardware (HW) accelerators as well as challenges, requirements, and emerging trends in AI accelerators for future autonomous vehicles (FAVs).

Abstract
Growing interests in designing neural networks with analog memory devices and circuits has been ignited, recently. Accurate simulations to verify the performance of the embedded neural networks are required before fabricating a chip. However, deep neural networks are composed of a ton of parameters such as weights and biases, and it leads to simulating a whole system with classical circuit simulators impossible. To cope with the difficulty, functional modeling-based simulators using high-level programming languages have been proposed. However, there exist unexpected errors in approximated simulation results compared to those of classical circuit simulators. In addition, they can only support a limited range of memory devices and circuits. Motivated from these limitations, statical modeling-based simulators has been suggested. They can emulate the unexpected dynamics of the system as they have the ability to represent non-analytic dynamics of memory devices and circuits. In this talk, we introduce various types of existing simulation methods and challenges for designing statistical modeling-based methods in relation to promising deep learning models such as physics-informed neural networks and Neural ODE.

Abstract
When we design an SoC or a multi-die IC consisting of 3rd-party IPs, heterogeneous components, or functional dice, synchronization of the clock signals across all of them could be a headache. Fortunately, Delay-Locked Loop (DLL) comes to the rescue. However, a DLL is traditionally built with some analog circuitry inside and thus making the design process complicated if not mysterious for system integrators. The emergence of cell-based DLL design style over the past two decades has alleviated this problem greatly. A cell-based DLL design is not only small and easy-to-design, but also robust to the process and temperature variation. Also, it could lend itself to automation as a DLL compiler and so one can generate a DLL instance on the push of a button. In this tutorial, we will take on a step-by-step journey to show you how to make your own DLL easily using only standard cells. Specific topics such as phase detector, tunable delay line, phase-locking procedure, coping strategy for process and temperature variation, and duty-cycle correction will be covered in detail.

Abstract
Posit is designed as an alternative to IEEE 754 floating-point format for many applications. With the same bit-width, it can provide a much larger dynamic range than IEEE floating-point format. In addition, posit has non-uniformed number distribution. This distribution fits well with the data distribution of deep learning and signal processing applications. Due to these advantages, posit format is nowadays popular in these applications. Many posit based arithmetic units and posit based deep learning accelerator have been proposed in the literature. However, due to the dynamic component bit-width, the cost of posit computation is still higher than the floating-point counterpart. There are many optimizations that can potentially be investigated to reduce its hardware cost. In this tutorial, the posit format and posit based arithmetic units will be first discussed. Then, several state-of-the-art posit based deep learning accelerator designs will be presented. And finally, the challenges and future research directions will be discussed to motivate more related research works.

Abstract
Energy-efficient computing architectures are imperative to employ AI systems at battery-powered edge devices. Although von Neumann architecture can support various tasks, it requires excessive power consumption to conduct massive matrix-vector multiplications (MVM) for AI systems, thereby precluding applications in edge intelligence. As a solution to the strict power budget at edge devices, neuromorphic computing and computing-in-memory (CIM) architectures have gained importance. In this talk, I will introduce approaches in neuromorphic computing and CIM architectures for edge intelligence. In particular, I will discuss a neuromorphic simultaneous localization and mapping (SLAM) accelerator employing oscillator-based pose-cells inspired by spatial recognition of rodents, and a resistive RAM (RRAM)-based CIM architecture surmounting technological challenges of RRAM.