Systematic Design of Timing Circuits
Prof. Asad A. Abidi
Asad Abidi received the BSc degree in Electrical Engineering from Imperial College, London in 1976, and the PhD from the University of California, Berkeley in 1982. He worked at Bell Laboratories, Murray Hill until 1985, and then joined the faculty of the University of California, Los Angeles where he is Distinguished Chancellor’s Professor of Electrical Engineering. With his students he has developed many of the radio circuits and architectures that enable today’s mobile devices.
Among other awards, Professor Abidi has received the 2008 IEEE Donald O. Pederson Award in Solid-State Circuits and the 2012 Best Paper Award from the IEEE Journal of Solid-State Circuits. The University of California, Berkeley’s Department of EECS recognized him as a Distinguished Alumnus in 2015. He was elected Fellow of IEEE in 1996, Member of the US National Academy of Engineering, and Fellow of TWAS, the world academy of sciences.
The design science of circuits has advanced to the point that op amps and A/D converters can be designed optimally on first silicon with a minimum of effort, but with considerable insight.
But electronics uses many circuits that work in the time domain. There, only the design science of LC oscillators has reached maturity.
A large class of timing circuits employs delay stages, such as Ring Oscillators and Delay-Locked Loops. In this talk I will show new results that allow accurate, first time-right design for Phase Noise, Random and Deterministic Jitter, and Spectral Spurs. I will show a systematic design methodology that uses these circuits to realize a wireless quality fractional-N frequency synthesizer.
Memory Controller Technology for the Data Driven New Normal
Dr. Jin-Hyeok Choi
Jin-Hyeok Choi, Executive Vice President of Memory business of Samsung Electronics Co. Ltd, is currently leading the Solution Product R&D, which delivers flash storage products ranging from mobile memory device of eMMC and UFS to client, server, and enterprise class SSDs.
He received his B.S., M.S., and Ph. D. degrees from Seoul National University, in 1989, 1991, and 1996, respectively, all in electronic engineering. He also studied low power circuits at the Institute of Industrial Science in the University of Tokyo, Japan.
He joined Samsung Electronics in 2003 as a SoC design engineer, where he was involved in developing mobile storage. From 2012 to 2019, he was in charge of the Controller Development Team. Controller is core component of solution product based on NAND Flash. He developed and commercialized eMMC and UFS for the first time in the world. He also developed various controllers for SATA/SAS/NVMe SSDs.
He developed the enterprise premium SSD with high endurance VNAND for the first time, and has contributed on the expansion of the storage market and continuously been leading the technology in the storage area. Since December 2019, he has been a head of Solution Product & Development of Memory Division of Samsung Electronics.
In the era of Covid-19 New Normal, our daily activities are rapidly moving from off-line to on-line. Recent advancements in high speed network, AI / machine learning, and high-performance computing helped this transition successfully, thus enabling many data-driven services/products such as online business, autonomous vehicles, metaverse, and etc. However, the data generated from daily life continued to increase exponentially, accompanied with the growing need for higher capacity & performance in storage, computation, and transmission. Data centers those are responsible for massive data storage, have dramatically increased the storage capacity & performance by extensive usage of non-volatile memory-based storage systems. However, such an improvement of capacity & performance has inevitably led to the increase in the power consumption, thus bringing the limited power budget as a system performance constraint. To solve this problem, the storage devices actively use new architectural techniques, such as hardware acceleration and in-storage processing, as well as new power-efficient components fabricated with advanced semiconductor technology. In addition, the server systems also try to achieve power efficiency by using new interface technology such as CXL, which improved the way data is transferred between processors, memory and storage. In this presentation, we first introduce our non-volatile memory storage products & technology, and then explain our approach to achieve power efficiency used in storage architecture & design. Lastly, we present the next-generation storage systems, including SSDs with CXL interface.
Neural recording with high-channel count microelectrode arrays: When size matters
Prof. Manuel Delgado-Restituto
Manuel Delgado-Restituto received the Ph.D. degree in Electronic Physics (Honors) from the University of Seville, Spain, in 1996. Since then, he has been working with the Institute of Microelectronics of Seville (IMSE-Univ. of Sevilla) where he currently heads a research group on low-power medical microelectronics and works in the design of silicon and optoelectronic microsystems for understanding biological neural systems, the development of neural prostheses and brain-machine interfaces, the implementation of wireless body area network transceivers and the realization of RFID transponders with biomedical sensing capabilities.
Manuel has co-authored 2 books, more than 20 chapters in contributed books, and some 200 articles in peer-review specialized publications. He also holds 7 patents.
Manuel seved as an Associate Editor for different IEEE Publications (TCAS-I, TCAS-II and TBioCAS) and as Editor-in-Chief for the IEEE JOURNAL on EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS. He also served as Vice President for Publications of the IEEE Circuits and Systems Society and now is serving as President-Elect of this Society. He has also served (or is serving) in the Organizing Committee of different international conferences, including his role as General co-Chair for ISCAS 2020 and as Technical Program co-Chair of ISCAS 2022.
Neuroscience research into how complex brain functions are implemented at a extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces towards employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this area consumption burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this talk, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and point out to strategies for improving performance.
Yangsung Joo is leading the Design Research Lab, SK Hynix. The Lab is developing next LPDDR & DDR DRAMs and researching next memory and solutions. He had worked at numerous memory development projects in global firms, since he received the Master degree in Electrical Engineering from the Korea University, in 1992.
Data creation is constantly happening in our world at the enormous rate of growth, throughout the systems such as from the small devices to the larger scale Data Centers. Data ecosystems, where these data are expanding to maintain and sustain our daily lives, have required the much more efficient and effective processing. In order to meet the demands, memory industry has kept scaling up the density, bandwidth and energy efficiency. However, the DRAM industry is facing serious challenges on keeping the scaling trends. Actually, the slower phase in conventional system developments has already been seen by the markets. As most of semiconductor and system industries are pursuing economically optimal solutions, a lot of evolutionary and revolutionary project papers have been published. This talk will show those interesting researches including SK Hynix pathfinding activities, and bring forward collaboration opportunities to the academia and industrial frontiers.